Subject: [Coin] FW: IPv6 Switch ML @ IETF 105 Hackathon

From: <[email-masked]>
Date: Fri, 24 Jan 2020 19:44:23 -0500

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Hemant

From: [email-masked] <[email-masked]> 
Sent: Friday, January 24, 2020 7:38 PM
To: [email-masked]; [email-masked]
Subject: RE: [Coin] IPv6 Switch ML @ IETF 105 Hackathon

An update:

The second problem listed in the email below, viz., runtime index of array,
is solved.

The open-source P4 compiler (p4lang/p4c) and simple_switch simulator
(p4lang/behavioral-model) were changed to support runtime index for an
array.  I changed p4c and Antonin Bas changed the simple_switch.   I expect
to check in code to p4c early next week.  Simple_switch code is already
checked in. 

The software can be added to a FPGA.  Then switch-ML could run on smartNIC
using a FPGA.  Just add a home hub or switch to the smartNIC port and one
has at least 8-10 hosts running switch-ML with the smartNIC.  Now, a
graduate student can write switch-ML code. 

No switching or routing asic supports a runtime index for an array.  It's
now up to asic vendors to support the feature.

For the Vancouver IETF, I don't see why we can't complete the switch-ML
P4-16 software and use the simple_switch and mininet hosts to run switch-ML.
Unfortunately, I am busy with other compiler work, so others can just use
runtime index and the parser trick included below and develop the P4 code.

We try and write production quality code for the P4 compiler.  Here are some
examples of runtime array indices tested with new code.

hdr.vector[hdr.ml.idx1 - (hdr.ml.idx2 >> 8w1)].e =
hdr.ethernet.etherType[15:8] + 7;

hdr.ethernet.etherType[7:0] = hdr.vector[(hdr.ml.idx2 ^ 8w0x07) & 8w0x7].e;

hdr.vector[hdr.vector[hdr.ethernet.dstAddr[39:32] & 8w0x7].e & 8w0x7].e =
hdr.ethernet.dstAddr[47:40];

If the runtime index exceeds array bounds, the simulator will crash. 

Hemant

From: Coin <[email-masked] <mailto:[email-masked]> > On Behalf
Of [email-masked] <mailto:[email-masked]> 
Sent: Sunday, July 21, 2019 6:14 AM
To: [email-masked] <mailto:[email-masked]> 
Subject: [Coin] IPv6 Switch ML @ IETF 105 Hackathon

I ran into interesting issues writing Algorithm 1 from
https://arxiv.org/pdf/1903.06701.pdf  at the hackathon yesterday.  It would
be good for any author of the paper to chime in.

First, I have read several research papers using P4 which publish P4 or
pseudo P4 code in the paper.  The switch ML paper does not.  It would have
been good to publish the code because P4 is jumping through hoops
implementing Algorithm 1 for switch with bmv2 simulator.  I used
public-domain p4lang/p4c and its bmv2 simple_switch simulation to test P4
code at the hackathon.

I used a P4 header stack (array) to represent the vector.  P4 has no for
loops, so how does one add elements of the vector? There is the one way.
You can have one action that adds 1 header, another that adds 2, another
that adds 3, etc., and choose between them at run time via a table lookup.
Even with a vector with 20-50 elements, writing such P4 code manually is
risky.  One has to write a Python script to generate such code.  The paper
did not think of it, but an alternative exists.  With every element in the
vector, use a new 1-byte field.  The field has values 0 or 1.  1 represents
bos (bottom of stack) like what MPLS uses.  The last element has bos set to
1.  Then, one has a termination condition in the P4 parser to terminate
recursive parsing of vector.  As the parser is recursing through the vector,
add the vector elements and save sum in metadata.  I didn't use a bit for
bos because the p4c bmv2 model accepts a header on byte boundary.  I plan to
add such details to my draft in the next revision:
https://datatracker.ietf.org/doc/html/draft-hsingh-ipv6-coin-ml  

The same p4c bmv2 model, also, does not accept an index into array if the
index is a run-time value.  The p4-16 specification allows run-time index.
Algorithm 1  in the paper uses p.idx which is a run-time value.  Again, one
has to use P4 tables.  Include the run-time variable index as a table search
key, which selects between several different actions that are identical,
except for the constant array index values they use.  This gets crazy with
128 or 512 indices in the paper.  Again, one would have to generate P4 code
to avoid mistakes cut-and-pasting code.  For 128 indices with some bit
shifting, maybe we reduces indices to 32.   If the Barefoot Tofino asic
allows run-time index into array, then it's better to use Tofino simulator
rather than bmv2 simulator.

I am not working in the hackathon today.  I have personal matters to take
care of on Sunday.

Hemant