Subject: OHCI ! Bewildering queries :)

From: Vasudev Mulchandani <[email-masked]>
Date: Wed, 19 May 1999 06:12:29 MDT

Hello FireWorkers !!

Scratching heads for long lead to this option !!

Currently working on OHCI Adapters !

The test setup has two nodes on 1394 bus and its corresponding
device drivers. The LPS bit and link enable are set in the HCControl Register
in the increasing order.

A bus reset by two methods

a) is initiated by writting 0x20000 in Int Event Reg
   Observation :
   -------------
   -> ISR for Bus Reset is invoked
   -> ISR for unrecoverable error (for AT Request) is invoked
      dead bit set in ATRequest Context Ctrl Reg (contents = 0x0000880e)
   -> ISR for unrecoverable error (for ATResponse) is invoked
      dead bit set in ATResponse Context Ctrl Reg (contents = 0x0000880e)

   Queries
   -------
   i) Since we haven't setup any DMA Descriptors for Transmit, how
      does the run bit get set for these contexts. does the host
      controller expect a DMA descriptor by default ?
   ii) What can cause an unrecoverable error ? The OHCI spec specifies
      one reason to be DEAD BIT being set in the DMA Engine. what are the
      the others, if any.

b) is initiated by writting 0x417f into PHY Register 0x01
   Observation:
   ------------
   -> ISR for bus reset is invoked.
      The s/w attempts to clear the Bus Reset bit in the int event clear
      register, but it doesnot get cleared
   -> as a result ISR is invoked again
      now the Bus Reset bit gets cleared
   -> a PHY Reg received Interrupt is received and its ISR is invoked

   Query:
   ------
   i) OHCI spec states that PHY reg received interrupt occurs only
      when a PHY reg is read through OHCI PHY Control register.
      BUT WE GET A PHY REG RECEIVED INTERRUPT WHEN WE WRITE INTO A
      PHY REGISTER.
      Is this valid ?? :)) ??

Thanx a lot for patiently reading these scenarios and incase you can
enlighten us, we did be greatly blessed !!

Eagerly awaiting a reply, from the gallery of experts out there !!

Adios

--vasu

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---

From: Robert Macomber <[email-masked]>
Date: Wed, 19 May 1999 11:35:33 -0400

Hi Vasu,

A better place to ask Open HCI questions is on [email-masked].
There are lots of OHCI users and implementers on that reflector.

comments embedded below...

> a) is initiated by writting 0x20000 in Int Event Reg

This is what would happen if the RUN bits were set without a valid command
pointer (specifically a non-zero Z value).  The bus reset event is used
to hold off operation of the AT contexts.  It could be that the
implementation you're using does some strange things when bus reset is
written by software.  Setting the event bits, though allowed, is probably
infrequently done.

> b) is initiated by writting 0x417f into PHY Register 0x01

The reason for being unable to clear the bus reset bit is probably that
the self ID phase hasn't completed yet.  The bus reset bit cannot be
cleared until the self ID complete bit has also become set.

It looks to me like the phy reg receive event is probably getting set
when the autonomous read of register zero occurs.  This is technically
incorrect as nothing is available to read in the phy control register.
The rules for avoiding reads to offset 0 were formulated late in the
game.  The implementation you're using probably wasn't updated to
have automonous reads NOT set the phy reg receive event.

--
Robert L. Macomber
National Semiconductor Corporation
Email: [email-masked]
Phone: 207-541-4677, Fax: 207-541-6108