Subject: Re: A doubt on selfID processing!!!

From: venkatesh v <[email-masked]>
Date: Tue, 25 May 1999 20:47:12 -0700

Hello raj,
Thanx for responding to my queries. My order of initialization sequence
is as follows:
1) Clear the Interrupt mask register so that no interrupts come during
init.
2) Set the LPS bit.
3) Set the cycler timer enable bit in linkcontrol register
4) Set the PhyreqResourcesAllBit in PhysicalRequestFilterHi register.
5) set the noByteSwapDataBit to zero
6) Enable posted writes by setting postedwriteenable bit in HCCOntrol
register
7) Allocating memory for configROM and writing into ConfigROMMap
register
8) Setting the linkenable bit in HCControl register

9)Then allocate memory for selfID buffer by using memalign so that i
get a 2K byte aligned memory.
10) Writing this allocated address into selfID buffer register. Then
enabling the rcvselfid bit in LinkControl register.

I think i am writing a valid physical address into the selfId buffer
register since i am able to dump its contents in the wind shell.
I am clearing the bus reset bit in ISR. and i havent got the selfID
complete interrupt so far.

Eagerly awaiting a reply from u,

Rgds,
venkat

--- Nagaraj G <[email-masked]> wrote:
> Hi Venkat,
>
> Question 1) What other reg in isters you are
> initializing before programming the
> selfIDBuffer register?
> Question 2) Are you writing a valid Physical address
> into selfIDBuffer
> register?
> Question 3) Are you clearing the busReset &
> selfIDComplete bits in the ISR?
>
> Hope to get reply for helping you.
>
> Raj
>
> -----Original Message-----
> From: IETF IP over 1394 Working Group
> [mailto:[email-masked]]On Behalf Of
> venkatesh v
> Sent: Tuesday, May 25, 1999 6:47 PM
> To: [email-masked]
> Subject: A doubt on selfID processing!!!
>
>
> Hi 1394 gurus,
> I am developing a 1394 OHCI device driver. In the
> initialization phase,
>
> Firstly i set the LPS bit and enable the Link-PHY
> communication.
> Then after some register initializations, i allocate
> a 2K aligned
> memory for Selfid Buffer, write the address of the
> allocated memory
> into the offset 0x64 (selfIDBuffer). Then i set the
> rcvselfid bit in
> LinkControl set register(offset : 0xe0).
>
> Now if i try to generate a bus reset interrupt by
> writing IBR=1 in the
> PHY register, the ISR for Bus reset is not invoked &
> the initialization
> procedure hangs.
> But suppose i dont set the rcvselfidbit, then the
> ISR gets invoked and
> bus reset is propagated across the bus. it is to be
> noted that there
> are only 2 nodes connected in the bus.
>
> Does this rcvselfid bit have any other significance
> otehr than enabling
> the RcvselfidDMA???
>
> Eagerly awaiting a reply....
>
> Rgds,
> Venkat....
>
>
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===

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---

From: Nagaraj G <[email-masked]>
Date: Wed, 26 May 1999 09:27:12 +0530

Hello Venkat,

Almost all steps seem OK. Just move the step 8 (setting linkEnable bit) to
the end, i.e., after the rcvSelfID bit setting and intoduce a step to
INITIATE BUS RESET by writing into PHY Register 01 through phyControl
register. It should work. I would also like to tell you that you can't clear
the busReset bit in the intEvent register until you get the selfIDComplete
interrupt. i.e., you can clear the busReset interrupt event only in your
selfIDComplete handler.

Rgrds,
Raj

-----Original Message-----
From: venkatesh v [mailto:[email-masked]]
Sent: Wednesday, May 26, 1999 9:17 AM
To: [email-masked]
Cc: [email-masked]
Subject: Re: A doubt on selfID processing!!!

Hello raj,

Rgds,
venkat

===