Subject: [rohc] Bug in bytecode of Simplified LZ77

From: [email-masked]
Date: Fri, 15 Oct 2004 13:40:20 +0530

Hi,

      Reference <draft-ietf-rohc-sigcomp-user-guide-00.txt>

In the Section 4.1 of the draft mentioned above input-bit- register label
is missing. There should always be a input-bit-register at 68-69 memory
address
in the UDVM.
      Therefore the bytecode generated by a parser is wrong. Decompression
failure will occur when decompression pointer (LSB) is not in the range of
0 to 7.

Any pointers and comments are welcome.

Regards
Saurabh
Hughes Software System
www.hssworld.com

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From: "Lajos Zaccomer (IJ/ETH)" <[email-masked]>
Date: Fri, 15 Oct 2004 12:28:59 +0200

Hi Saurabh,

First of all, there is a version 1 of the user guide document, but this is not important regarding your problem.
Second, the input bit order register is checked when INPUT-BITS or INPUT-HUFFMAN instructions are executed. After setting the decompressed pointer (that in this case has the same address as of the input bit order register), no such instructions can be found, thus no decompression failure would occur.

See also section 8.2 in RFC 3320:
Note that the INPUT-BITS and INPUT-HUFFMAN instructions retrieve a
   stream of individual compressed bits from the dispatcher.  To provide
   bitwise compatibility with various well-known compression algorithms,
   the input_bit_order register can modify the order in which individual
   bits are passed within a byte.

br/Zacco

-----Original Message-----
From: [email-masked] [mailto:[email-masked]]On Behalf Of [email-masked]
Sent: Friday, October 15, 2004 10:10 AM
To: [email-masked]
Subject: [rohc] Bug in bytecode of Simplified LZ77

Hi,

Regards
Saurabh
Hughes Software System
www.hssworld.com